中文说明：五级流水CPU设计 流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器会写（WB）五级，对应多周期的五个处理阶段。一个指令的执行需要5个时钟周期，每个时钟周期的上升沿来临时，此指令所代表的一系列数据和控制信息将转移到下一级处理。
English Description：
Five stage pipeline CPU design pipeline is a method to improve system stability and speed in digital system, which is widely used in high-end CPU architecture. According to the characteristics of MIPs processor, the whole process is divided into five stages: instruction fetch (if), instruction decoding (ID), execution (Ex), memory access (MEM) and register write (WB), which correspond to five processing stages of multi cycle. The execution of an instruction needs five clock cycles. When the rising edge of each clock cycle comes, a series of data and control information represented by the instruction will be transferred to the next level for processing.